Novel Design Methodology Using $L_{\bf EXT}$ Sizing in Nanowire CMOS Logic

@article{Kaushal2014NovelDM,
  title={Novel Design Methodology Using \$L_\{\bf EXT\}\$ Sizing in Nanowire CMOS Logic},
  author={Gaurav Kaushal and Sanjeev Kumar Manhas and Satish Maheshwaram and Bulusu Anand and Sudeb Dasgupta and Navab Singh},
  journal={IEEE Transactions on Nanotechnology},
  year={2014},
  volume={13},
  pages={650-658}
}
In this paper, the impact of nanowire source/drain extension, diameter, and channel length on nanowire (NW) device performance is investigated. We present a novel approach using the extension length as tuning parameter to match the drive current of n- and p-FET in NW CMOS logic applicable down to 10-nm gate length. Our approach overcomes the drive matching issue in NW/FinFET based CMOS circuits. We show that, in comparison to conventional CMOS, where the number of NWs/fins in p-FET is used to… CONTINUE READING
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