Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)

@article{Takeuchi2009NovelCO,
  title={Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)},
  author={Kai Takeuchi},
  journal={IEEE Journal of Solid-State Circuits},
  year={2009},
  volume={44},
  pages={1227-1234}
}
  • Kai Takeuchi
  • Published 2009 in IEEE Journal of Solid-State Circuits
As the cell size of the NAND flash memory has been scaled down by 40%-50% per year and the memory capacity has been doubling every year, a solid-state drive (SSD) that uses NAND as mass storage for personal computers and enterprise servers is attracting much attention. To realize a low-power high-speed SSD, the co-design of NAND flash memory and NAND controller circuits is essential. In this paper, three new circuit technologies, the selective bit-line precharge scheme, the advanced source-line… CONTINUE READING
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