Novel Approach to Reduce Source/Drain Series and Contact Resistance in High-Performance UTSOI CMOS Devices Using Selective Electrodeless CoWP or CoB Process

Abstract

This letter reports a selective metal deposition process using an electrodeless technique for MOSFETs fabricated in an ultrathin silicon-on-insulator (UTSOI) substrate. A layer of metal (CoWP or CoB) is formed on the source and drain nickel and cobalt silicides without depositing on the dielectric spacers. Leakage current information, which is an indication… (More)

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Cite this paper

@article{Pan2007NovelAT, title={Novel Approach to Reduce Source/Drain Series and Contact Resistance in High-Performance UTSOI CMOS Devices Using Selective Electrodeless CoWP or CoB Process}, author={James Pan and A. Topol and I. Shao and Chun-Yung Sung and J. Iacoponi and Ming-Ren Lin}, journal={IEEE Electron Device Letters}, year={2007}, volume={28}, pages={691-693} }