Noise and Spurious Tones Management Techniques for Multi-GHz RF-CMOS Frequency Synthesizers Operating in Large Mixed Analog-Digital SOCs
- Adrian Maxim
- EURASIP J. Wireless Comm. and Networking
A low phase noise multi-rate OC192 LC oscillator was realized in 0.13 μm CMOS. To minimize the gain of the oscillator, the frequency is first calibrated to within ±0.1% of the target value using a capacitor switching network and then the final locking is achieved with a PLL loop that controls a ±1% tuning range accumulation MOS varactor bank. The oscillator uses an NFET-only, constant bias voltage amplifier that eliminates the tail current source. A high PSRR and low 1/f and thermal noise regulator, based on a V/sub GS//R current, was used to bias the oscillator. The LC-VCO specifications include: phase noise <-115 dBc/Hz at 100 kHz offset, 40 kHz 1/f/sup 3/ corner frequency, <10 mA current consumption from a 3.3 V supply and 250×400 μm/sup 2/ die area.