Notice of Violation of IEEE Publication Principles<BR>A 9.953/10.7/12.5 GHz 0.13 &#x003BC;m CMOS LC oscillator using capacitor calibration and a V/sub GS//R based low noise regulator

  • Adrian Maxim
  • Published 2005 in
    2005 IEEE Radio Frequency integrated Circuits…

Abstract

A low phase noise multi-rate OC192 LC oscillator was realized in 0.13 &#x003BC;m CMOS. To minimize the gain of the oscillator, the frequency is first calibrated to within &#x000B1;0.1% of the target value using a capacitor switching network and then the final locking is achieved with a PLL loop that controls a &#x000B1;1% tuning range accumulation MOS varactor bank. The oscillator uses an NFET-only, constant bias voltage amplifier that eliminates the tail current source. A high PSRR and low 1/f and thermal noise regulator, based on a V/sub GS//R current, was used to bias the oscillator. The LC-VCO specifications include: phase noise <-115 dBc/Hz at 100 kHz offset, 40 kHz 1/f/sup 3/ corner frequency, <10 mA current consumption from a 3.3 V supply and 250&#x000D7;400 &#x003BC;m/sup 2/ die area.

Cite this paper

@article{Maxim2005NoticeOV, title={Notice of Violation of IEEE Publication Principles
A 9.953/10.7/12.5 GHz 0.13 μm CMOS LC oscillator using capacitor calibration and a V/sub GS//R based low noise regulator}, author={Adrian Maxim}, journal={2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers}, year={2005}, pages={411-414} }