Non-volatile memory reduction based on 1-D memory space mapping of a specific set of QC-LDPC codes


Supporting a great diversity of multi-rate H-matrices for multiple communication protocols requires a large amount of non-volatile memory, which may consume a large silicon area or logic elements and constrain the implementation of an overall decoder. Therefore, schemes for memory reduction are necessary to make the paritycheck storage more compact. This… (More)
DOI: 10.1186/1687-1499-2012-191


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