Optimal Control of Discrete Event Systems with Weakly Hard Real-Time Constraints
The rapid progress in high-performance microprocessor design has made it diicult to adapt real-time scheduling results to new models of microprocessor hardware, thus leaving an unfortunate gap between real-time scheduling theory and its practice. In light of current and expected trends in commercial microprocessor architecture design, it is therefore important to make a qualitative assessment of how modern processor architectures contribute to this gap. This paper addresses the problem of how to schedule periodic, real-time threads on a class of architectures referred to as multi-level-context (MLC) architectures. Examples of such architectures are real-time operating systems with support for user-or kernel-level threads, and multithreaded microprocessors endowed with on-chip contexts. A common feature of these architectures is that they provide support for the administration of threads within contexts at diierent levels of abstraction. Therefore, the cost for switching between threads will depend on the aanity of their corresponding contexts. The main contributions of this paper are to demonstrate (i) how the scheduling performance (in terms of success ratio) for oo-line scheduling on MLC architectures can beneet from an integrated heuristic that is cognizant of both the time-criticality of a thread and the current context aanity; and (ii) how the predicted performance for on-line scheduling on MLC architectures can beneet from an oo-line schedulability test that accounts for dynamic changes in the context aanity at run-time.