Noise shaping techniques for analog and time to digital converters using voltage controlled oscillators
@inproceedings{Straayer2008NoiseST, title={Noise shaping techniques for analog and time to digital converters using voltage controlled oscillators}, author={Matthew Z. Straayer}, year={2008} }
Advanced CMOS processes offer very fast switching speed and high transistor density that can be utilized to implement analog signal processing functions in interesting and unconventional ways, for example by leveraging time as a signal domain. In this context, voltage controlled ring oscillators are circuit elements that are not only very attractive due to their highly digital implementation which takes advantage of scaling, but also due to their ability to amplify or integrate conventional…
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References
SHOWING 1-10 OF 81 REFERENCES
1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS
- EngineeringIEEE Transactions on Circuits and Systems II: Express Briefs
- 2006
A 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver.
A CMOS time-to-digital converter with better than 10 ps single-shot precision
- Computer ScienceIEEE Journal of Solid-State Circuits
- 2006
A high-precision CMOS time-to-digital converter IC has been designed based on a counter and two-level interpolation realized with stabilized delay lines that reduces the number of delay elements and registers and lowers the power consumption.
Statistical Linearity Calibration of Time-To-Digital Converters Using a Free-Running Ring Oscillator
- Engineering2006 15th Asian Test Symposium
- 2006
Precise and fast time measurements have many applications in test that can be covered cost effectively by vernier delay line (VDL) based time-to-digital converters (TDC), implemented fully digitally…
An all-digital analog-to-digital converter with 12-μV/LSB using moving-average filtering
- Computer ScienceIEEE J. Solid State Circuits
- 2003
The combination of this ADC and a digital filter that follows can eliminate an analog prefilter to prevent the aliasing before A/D conversion and it is an ideal means to lower the cost and power consumption.
A Low-Cost Low-Power CMOS Time-to-Digital Converter Based on Pulse Stretching
- EngineeringIEEE Transactions on Nuclear Science
- 2006
A low-cost and low-power CMOS time-to-digital converter (TDC) with 50-ps time resolution is proposed in this paper. The reference clock frequency of the TDC is 80 MHz and the input range is…
All-digital PLL and transmitter for mobile phones
- Computer ScienceIEEE Journal of Solid-State Circuits
- 2005
The first all-digital PLL and polar transmitter for mobile phones is presented, exploiting the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom.
A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line
- Engineering, Computer ScienceIEEE Journal of Solid-State Circuits
- 2000
Test results show that even higher resolutions can be achieved using the VDL method, and resolutions down to 5 ps are demonstrated to be obtainable.
A Design-Optimized Continuous-Time Delta–Sigma ADC for WLAN Applications
- Computer ScienceIEEE Transactions on Circuits and Systems I: Regular Papers
- 2007
A third-order continuous-time delta-sigma (DeltaSigma) analog-to-digital converter (ADC) is presented and it is shown that GmC integrators are preferred over RC integrators in the low-pass filter of the modulator because they show a better tradeoff between power, speed, and accuracy.
A flexible multi-channel high-resolution time-to-digital converter ASIC
- Engineering2000 IEEE Nuclear Science Symposium. Conference Record (Cat. No.00CH37149)
- 2000
A data driven multi-channel time-to-digital converter (TDC) circuit with programmable resolution (/spl sim/25 ps-800 ps binning) and a dynamic range of 102.4 /spl mu/s has been implemented in a 0.25…
Only digital technology analog-to-digital converter circuit
- Engineering, Computer Science2003 46th Midwest Symposium on Circuits and Systems
- 2003
The proposed fully digital ADC is suitable for sensor applications and is designed and simulated using 0.5/spl mu/m CMOS parameters.