Noise performance of 0.35-/spl mu/m SOI CMOS devices and micropower preamplifier from 77-400 K


MOS transconductance and white noise is described from weak through strong inversion to facilitate the design of a 0.35-/spl mu/m, partially-depleted silicon-on-insulator (SOI) CMOS micropower, low noise preamplifier. This analysis is extended to cryogenic temperatures where MOS subthreshold slope is reduced significantly from its expected value… (More)


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