Node-disjoint paths on the mesh and a new trade-off in VLSI layout

  title={Node-disjoint paths on the mesh and a new trade-off in VLSI layout},
  author={Alok Aggarwal and Jon M. Kleinberg and David P. Williamson},
  journal={SIAM J. Comput.},
A number of basic models for VLSI layout are based on the construction of node- disjoint paths between terminals on a multilayer grid. In this setting, one is interested in minimizing both the number of layers required and the area of the underlying grid. Building on work of Cutler and Shiloach (Networks, 8 (1978), pp. 253{278), Aggarwal et al. (Proc. 26th IEEE Symposium on Foundations of Computer Science, Portland, OR, 1985; Algorithmica, 6 (1991), pp. 241{255), and Aggarwal, Klawe, and Shor… 

Routing vertex disjoint Steiner-trees in a cubic grid and connections to VLSI

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    2016 Fourth International Symposium on Computing and Networking (CANDAR)
  • 2016
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    19th Design Automation Conference
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    Discret. Comput. Geom.
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