NiSi Schottky Barrier Process-Strained Si (SB-PSS) CMOS Technology for High Performance Applications

@article{Ko2006NiSiSB,
  title={NiSi Schottky Barrier Process-Strained Si (SB-PSS) CMOS Technology for High Performance Applications},
  author={C. H. Ko and H. W. Chen and T. J. Wang and T. M. Kuan and J. W. Hsu and C. Y. Huang and C. H. Ge and L. Lai and W. C. Lee},
  journal={2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.},
  year={2006},
  pages={80-81}
}
State-of-the-art process-strained Si (PSS) technology featuring single-NiSi Schottky source/drain (S/D) and ultra-thin gate oxide of 1.2 nm is demonstrated for Lgate down to 39 nm. +10% performance boost of Schottky-barrier (SB)-PSS NMOS, as compared to its non-Schottky counterpart, is demonstrated due to series resistance reduction of the silicide S/D and enhanced strain effects. Highest SB-PSS PMOS drive current of 821 muA/mum (at VD = -1.2V and Ioff = 100 nA/mum) is recorded when integrated… CONTINUE READING
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