• DOI:10.1109/CONECT.2003.1231470
• Corpus ID: 1799204

Nexus: an asynchronous crossbar interconnect for synchronous system-on-chip designs

@article{Lines2003NexusAA,
  title={Nexus: an asynchronous crossbar interconnect for synchronous system-on-chip designs},
  author={Andrew Lines},
  journal={11th Symposium on High Performance Interconnects, 2003. Proceedings.},
  year={2003},
  pages={2-9}
}

• Andrew Lines
• Published 15 September 2003
• Computer Science
• 11th Symposium on High Performance Interconnects, 2003. Proceedings.

Asynchronous circuits can provide an elegant and high performance interconnect solution for synchronous system-on-chip (SoC) designs with multiple clock domains. This 'globally asynchronous, locally synchronous' (GALS) approach simplifies global timing and synchronization problems, improving performance, reliability, and development time. Fulcrum Microsystems' SoC interconnect, 'Nexus', includes a 16 port, 36 bit asynchronous crossbar which connects via asynchronous channels to clock domain converters for each synchronous module. Each synchronous module has its own local clock domain, and can send a variable length burst of data to any other module. In TSMC's 130 nm LV low-K process, the system achieves 1.35 GHz at 1.2 V with less than 5 mm/sup 2/ area. Power scales linearly with bandwidth, from a few mW of leakage to 8 W at the peak 780 Gb/s cross-section bandwidth. Latency through the interconnect is 2 ns plus 1/2 to 2/3 clock cycles of the receiving module. This compares favorably with other SoC interconnect solutions that have less bandwidth, higher energy per transfer and longer latencies. Nexus is an innovative and comprehensive solution to the challenge of SoC interconnect.