Nexus: an asynchronous crossbar interconnect for synchronous system-on-chip designs

  title={Nexus: an asynchronous crossbar interconnect for synchronous system-on-chip designs},
  author={Andrew Lines},
  journal={11th Symposium on High Performance Interconnects, 2003. Proceedings.},
  • Andrew Lines
  • Published 15 September 2003
  • Computer Science
  • 11th Symposium on High Performance Interconnects, 2003. Proceedings.
Asynchronous circuits can provide an elegant and high performance interconnect solution for synchronous system-on-chip (SoC) designs with multiple clock domains. This 'globally asynchronous, locally synchronous' (GALS) approach simplifies global timing and synchronization problems, improving performance, reliability, and development time. Fulcrum Microsystems' SoC interconnect, 'Nexus', includes a 16 port, 36 bit asynchronous crossbar which connects via asynchronous channels to clock domain… 

Figures from this paper

NanoMesh: An Asynchronous Kilo-Core System-on-Chip
  • Jonathan TseAndrew Lines
  • Computer Science
    2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems
  • 2013
It required only a few man-months of effort to develop a complete gate-level design and physical floor-plan which can run simple C programs such as Dhrystone, and a test chip is expected in 2013.
An Efficient Clocking Scheme for On-Chip Communications
An efficient synchronizer for on-chip communication based on mesochronous clocking scheme that can endure frequency drift between two clock domains and saves around 74% of power consumption is proposed.
An asynchronous NOC architecture providing low latency service and its multi-level design framework
The proposed NOC protocol and its asynchronous implementation are presented as well as the multi-level modeling approach using SystemC language and transaction-level-modeling, which shows that the asynchronous NOC can offer 5 Gbytes/s throughput in a 0.13 /spl mu/m CMOS technology.
On-chip surfing interconnect
This thesis extends the application of surfing to on-chip interconnects and introduces surfing RC interconnect and surfing LC interconnect techniques and uses distributed varactors to dynamically vary the latency of LC interConnects and thus effect surfing.
A 72-Port 10G Ethernet Switch/Router Using Quasi-Delay-Insensitive Asynchronous Design
The design of a commercially-shipping 72-port 10G Ethernet switch router integrated circuit is presented, which relied heavily on a novel tool flow utilizing both commercial and proprietary EDA tools for automatic place-and-route of asynchronous layout.
Asynchronous Packet-Switching for Networks-on-Chip
Pet-switches play a key role in interconnection networks and this paper focuses on their implementation as asynchronous circuits and the results of experiments run to evaluate several aspects of the routing switch implementation are presented.
Serving the Montium : design of an energy-efficient processor-network interface
The CCU is part of the Chameleon architecture, a tile based system on chip consisting of several tiles and a network on chip and serves as an hardware interface between the network and a tile.
Modified bundled-data as a new protocol for NoC asynchronous links
A scalable delay insensitive asynchronous NoC with adaptive routing
An asynchronous NoC (ANoC) that features asynchronous links and asynchronous adaptive routing mechanism that outperforms the synchronous NoC especially when the NoC size becomes large.
Design Automation of Real-Life Asynchronous Devices and Systems
Four design flows are presented that can tackle large designs without significant changes with respect to synchronous design flow, and offer a trade-off from very low overhead, almost synchronous implementations, to very high performance, extremely robust dual-rail pipelines.


Energy and performance models for clocked and asynchronous communication
  • K. Stevens
  • Computer Science
    Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings.
  • 2003
Parameterized first-order models for throughput, energy, and bandwidth are presented which allow apples-to-apples comparisons against different design targets and pipeline methodologies and allow designers to understand tradeoffs between implementations that have a varying degree of timing assumptions and design requirements.
Delay insensitive system-on-chip interconnect using 1-of-4 data encoding
A delay-insensitive, asynchronous approach to interconnect over long paths using 1-of-4 encoded channels switched through multiplexers, which shows that it can provide a higher throughput than the simpler tristate bus while using a narrower datapath.
Efficient self-timed interfaces for crossing clock domains
This work presents implementations of STARI where the FIFO consists of a single, handshaking stage, and shows that the STARI interface can exploit the stability of typical clocks to achieve low latencies and negligible probabilities of synchronization failure using very simple hardware.
Pipelined Asynchronous Circuits
A design style for implementing communicating sequential processes (CSP) as quasi delay insensitive asynchronous circuits, based on the compilation method of [1], which can easily implement circuits with some slack between inputs and outputs is presented.
The design of an asynchronous MIPS R3000 microprocessor
The paper describes the structure of a high-performance asynchronous pipeline, in particular precise exceptions, pipelined caches, arithmetic, and registers, and the circuit techniques developed to achieve high throughput.
The limitations to delay-insensitivity in asynchronous circuits
Asynchronous techniques —that is, techniques that do not use clocks to implement sequencing— are currently attracting considerable interest for digital VLSI circuit design, in particular when the
Point to point GALS interconnect
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an asynchronous
Proceedings of the 8th International Symposium on Asynchronous Circuits and Systems
  • Proceedings of the 8th International Symposium on Asynchronous Circuits and Systems
  • 2002