New technique for testing of delay fault in cluster based FPGA


The recent trend of reconfigurable hardware and convergence of hardware platform in embedded system enhance application of FPGAs. Although the capability and performance of FPGA have advanced, the testing of FPGAs both online and off-line (manufacturer oriented testing) poses a major challenge. In this paper we have presented a BIST structure to test delay… (More)


5 Figures and Tables

Slides referencing similar topics