New low-power techniques: Leakage Feedback with Stack & Sleep Stack with Keeper


For the most recent CMOS feature sizes (e.g., 90 nm and 65 nm), leakage power dissipation has become an overriding concern for VLSI circuit designers. ITRS reports that leakage power dissipation may come to dominate total power consumption [1]. We are doing comparable analysis of different low power, leakage current reduction techniques like SLEEP approach… (More)


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