New considerations for MOSFET power clamps

Abstract

Two ESD clamp circuit design techniques have been developed to reduce cell size and to combat the effects of gate leakage that have become significant in recent generations of digital CMOS process technology. Such clamps have proven to be able to withstand HBM stresses of 6kV and CDM pulses of 1.2kV. 
DOI: 10.1016/S0026-2714(03)00123-9

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