New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults

  title={New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults},
  author={Ad J. van de Goor and Said Hamdioui and Georgi Gaydadjiev and Zaid Al-Ars},
  journal={2009 Asian Test Symposium},
Due to the rapid decrease of technology feature size speed related faults, such as Address Decoder Delay Faults (ADDFs), are becoming very important. In addition, increased leakage currents demand for improved tests for Bit Line Imbalance Faults (BLIFs)(caused by memory cell pass transistor leakage). This paper contributes to new and improved algorithms for detecting these faults. First it provides an improved version of existing GalPat algorithm and introduces two new algorithms to detect… CONTINUE READING
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Testing Semiconductor Memories, Theory and Practice, Com- Tex Publishing

  • A. J. van de Goor
  • Gouda, The Netherlands,
  • 1998
Highly Influential
5 Excerpts


  • T. Powell, A. Kumar
  • Rayhawk and N.Mukherjee, ’Chasing Subtle Embedded…
  • 2005
2 Excerpts


  • S. Hamdioui
  • Al-Ars, A.J. van de Goor, R Wadsworth, ’Impact of…
  • 2005
1 Excerpt

Self-Test Pattern to Detect Stuck-Open Faults

  • M. T. Fragano, J. H. Oppold, M. R. Ouellette, J. P. Rowland
  • US Patent No.: US 6,442,085
  • 2002
1 Excerpt

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