Network-on-chip (noc) architectures for exa-scale chip-multi-processors (cmps)

@inproceedings{Taskin2013NetworkonchipA,
  title={Network-on-chip (noc) architectures for exa-scale chip-multi-processors (cmps)},
  author={Baris Taskin and Ankit More},
  year={2013}
}

Citations

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Range-based dynamic routing of hierarchical on chip network traffic

  • 2014 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
  • 2014
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CITES BACKGROUND & METHODS
HIGHLY INFLUENCED

CATBR-Congestion Aware Traffic Bridging Routing among hierarchical networks-on-chip

  • 2016 29th IEEE International System-on-Chip Conference (SOCC)
  • 2016
VIEW 1 EXCERPT
CITES BACKGROUND

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