Negative Capacitance for Boosting Tunnel FET performance

Abstract

We have proposed and investigated a super steep subthreshold slope transistor by introducing negative capacitance of a ferroelectric HfO<sub>2</sub> gate insulator to a vertical tunnel FET for energy efficient computing. The channel structure and gate insulator are systematically designed to maximize the <inline-formula><tex-math notation="LaTeX"> $I_{{\rm… (More)

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