NaNet: a configurable NIC bridging the gap between HPC and real-time HEP GPU computing

Abstract

NaNet is a FPGA-based PCIe Network Interface Card (NIC) design with GPUDirect and Remote Direct Memory Access (RDMA) capabilities featuring a configurable and extensible set of network channels. The design currently supports both standard — Gbe (1000BASE-T) and 10GbE (10Base-R) — and custom — 34 Gbps APElink and 2.5 Gbps deterministic latency KM3link — channels, but its modularity allows for straightforward inclusion of other link technologies. The GPUDirect feature combined with a transport layer offload module and a data stream processing stage makes NaNet a low-latency NIC suitable for real-time GPU processing. In this 1Corresponding author. c © CERN 2015, published under the terms of the Creative Commons Attribution 3.0 License by IOP Publishing Ltd and Sissa Medialab srl. Any further distribution of this work must maintain attribution to the author(s) and the published article’s title, journal citation and DOI. doi:10.1088/1748-0221/10/04/C04011 2 0 1 5 J I N S T 1 0 C 0 4 0 1 1 paper we describe the NaNet architecture and its performances, exhibiting two of its use cases: the GPU-based low-level trigger for the RICH detector in the NA62 experiment at CERN and the on-/off-shore data transport system for the KM3NeT-IT underwater neutrino telescope.

Cite this paper

@inproceedings{Lonardo2015NaNetAC, title={NaNet: a configurable NIC bridging the gap between HPC and real-time HEP GPU computing}, author={Alessandro Lonardo}, year={2015} }