NXG06-3: The Central-stage Buffered Clos-Network to Emulate an OQ Switch

@article{Wang2006NXG063TC,
  title={NXG06-3: The Central-stage Buffered Clos-Network to Emulate an OQ Switch},
  author={Feng Wang and Wenqi Zhu and Mounir Hamdi},
  journal={IEEE Globecom 2006},
  year={2006},
  pages={1-5}
}
In this paper, we propose a highly scalable packet switch that is based on a multi-stage multi-layer architecture made up of many modest size switches. This new architecture resembles the famous Clos-network studied in circuit switching systems except that it has distributed shared memories in the central stage. We call it central-stage buffered Clos… CONTINUE READING