Multistack flip chip 3D packaging with copper plated through-silicon vertical interconnection

  title={Multistack flip chip 3D packaging with copper plated through-silicon vertical interconnection},
  author={R T Hon and S. W. Ricky Lee and S. X. Zhang and C. L. Wong},
  journal={2005 7th Electronic Packaging Technology Conference},
  pages={6 pp.-}
3D packaging (3DP) is an emerging trend as a solution for microelectronics development toward system in package (SiP). 3D flip chip stacking structures with through silicon vias (TSVs) have very good potential for the implementation of 3D packaging. In this study, a prototype of multistack flip chip 3D packaging with TSVs for interconnection is designed and fabricated. Processing techniques for prototype fabrication are studied and discussed in details. The formation of TSVs is by the deep… CONTINUE READING
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