Multiprocessor Validation of the Pentium Pro

@article{Marr1996MultiprocessorVO,
  title={Multiprocessor Validation of the Pentium Pro},
  author={Deborah T. Marr and Subramanian Natarajan and Shreekant S. Thakkar and Richard N. Zucker},
  journal={Computer},
  year={1996},
  volume={29},
  pages={47-53}
}
In the past, multiprocessor systems have taken a year longer than uniprocessor systems to introduce because of the need to develop and validate the additional functionality required for multiprocessor systems. Manufacturers, however, don't want to wait this long to release products using the latest multiprocessor systems. Our challenge in designing Intel's newest microprocessor, the Pentium Pro processor, was to eliminate the lag time. We wanted to accomplish this by introducing systems where… 
Pre-Silicon Validation of IPF Memory Ordering for Multi-Core Processors
  • Soohong P. Kim
  • Computer Science
    2005 Sixth International Workshop on Microprocessor Test and Verification
  • 2005
TLDR
The latest result showed that memory ordering specific focused tests and pseudo-random exercisers were very effective in finding memory ordering bugs in the pre-silicon validation stage of Intelreg Itaniumreg processor family (IPF) memory ordering.
Test Generation for CMP Designs
  • P. Singh, D. Landis
  • Computer Science
    2010 11th International Workshop on Microprocessor Test and Verification
  • 2010
TLDR
The MP test program coverage is estimated by simulating the tests on a simple software model of the cache coherence protocol and equations are extrapolated to predict coverage as a function of core count based on constraints on addresses and test size.
Static scheduling of multi-domain memories for functional verification
  • M. Kudlugi, C. Selvidge, R. Tessier
  • Computer Science
    IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281)
  • 2001
TLDR
This work describes new scheduling heuristics for memory-based designs with multiple asynchronous clock domains that are mapped to parallel verification systems and shows that when the technique is applied to an FPGA-based emulator containing 48MB of SRAM, evaluation fidelity is maintained and increased verification performance is achieved.
Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance Validation
TLDR
An approach for performance validation which uses semi-formal techniques rather than pure simulation for providing a wider coverage, actual RTL implementations wherever available for more accurate analysis, and sequential equivalence checking for validating the abstract models for IP's whose RTL is either not present or from which datapath has been abstracted out is presented.
Test Generation Approach for Post-Silicon Validation of High End Microprocessor
TLDR
This work uses the concept of building a Master Test Program that is used to build multiple test-streams by utilizing an instruction pool and a data pool to extend coverage of the processor state space while reducing the build time greatly.
Targeted random test generation for power-aware multicore designs
TLDR
Targeted random MP test generation techniques for multicore P-State functional verification are introduced and a simple coverage metric is developed to evaluate MP test effectiveness, and two new methodologies are formulates to set up and apply MP tests for effective multicoreP-State coverage.
Design Verification of the S3.mp Cache-Coherent Shared-Memory System
This paper describes the methods used to formulate and validate the memory subsystem of the cache-coherent Sun Scalable Shared-memory MultiProcessor (S3.mp) at three levels of abstraction: the memory
Fingerprinting: hash-based error detection in microprocessors
TLDR
In the Reunion execution model, this thesis shows that architectural fingerprints can detect both soft errors and input incoherence with complexity-effective redundant execution in a chip multiprocessor.
Postsilicon Validation Methodology for Microprocessors
A proposed methodology targets microarchitectural attributes prioritized based on the importance of validating corner cases. Several test templates cover all the critical attributes.
Snail Algorithm For Task Allocation In Mesh Networks
TLDR
This work is based on three very well known task allocation algorithms: First Fit, Frame Sliding and Adaptive Scan and also one new approach (author’s own idea based on the Adaptive scan approach) Snail Algorithm.
...
1
2
...

References

SHOWING 1-8 OF 8 REFERENCES
Multiprocessor design verification for the PowerPC 620 microprocessor
TLDR
In creating SCPG, the design complexity and frequent design changes were dealt with by abstracting areas of concern as simple languages, writing tools to generate tests, and executing these in the standard verification environment.
Architectural and multiprocessor design verification of the PowerPC 604 data cache
  • G. Cai
  • Computer Science
    Proceedings International Phoenix Conference on Computers and Communications
  • 1995
TLDR
The architecture and multiprocessor verification for the Power PC 604 data cache systematically checks the data cache architecture, logic, and implementation correctness and provides the assurance that the PowerPC 604 microprocessor's aggressive hardware and software implementation is carried out correctly in the uniprocessors and multip rocessor environment.
An overview of the Pentium Pro processor bus
TLDR
The Pentium Pro processor bus architecture team believes that it has laid the foundation for a processor bus that would still be viable for processors introduced later this decade and possibly beyond.
A 0.6 /spl mu/m BiCMOS processor with dynamic execution
  • R. Colwell, R. Steck
  • Computer Science
    Proceedings ISSCC '95 - International Solid-State Circuits Conference
  • 1995
TLDR
A next generation, Intel-Architecture compatible microproceesor with dynamic execution is implemented in 0.60 /spl mu/m 4-layer metal BiCMOS to allow complete access to all structures without the overhead of a full LSSD implementation.
The SPLASH-2 programs: characterization and methodological considerations
TLDR
This paper quantitatively characterize the SPLASH-2 programs in terms of fundamental properties and architectural interactions that are important to understand them well, including the computational load balance, communication to computation ratio and traffic needs, important working set sizes, and issues related to spatial locality.
Cache coherence protocols: evaluation using a multiprocessor simulation model
TLDR
The magnitude of the potential performance difference between the various approaches indicates that the choice of coherence solution is very important in the design of an efficient shared-bus multiprocessor, since it may limit the number of processors in the system.
Memory consistency and event ordering in scalable shared-memory multiprocessors
TLDR
A new model of memory consistency, called release consistency, that allows for more buffering and pipelining than previously proposed models is introduced and is shown to be equivalent to the sequential consistency model for parallel programs with sufficient synchronization.
Pentium Pro processor workstation/server PCI Chipset
  • Mike Bell, T. Holman
  • Computer Science
    COMPCON '96. Technologies for the Information Superhighway Digest of Papers
  • 1996
The 82450GX PCI Chipset provides a high performance memory subsystem and PCI bridge solution for workstation and server Pentium Pro processor based systems. This paper describes the architecture,