Multiprocessor System on Chip based on programmable processor cores Nios II Altera

@inproceedings{Iryna2013MultiprocessorSO,
  title={Multiprocessor System on Chip based on programmable processor cores Nios II Altera},
  author={Klymenko Iryna and Alexander Storozhuk},
  year={2013}
}
The features of a standard design flow facilities SOPC Builder Altera to develop multiprocessor systems are considered. Modeling and research of programmable multiprocessor cores NIOS II Altera, which are designed for high-performance control functions are completed. Кеу words – Multiprocessor System on Chip, System on a Programmable Chip Builder, Field-Programmable Gate Array, processor cores Nios II Altera, design flow, Cyclone II. 

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