Multiprocessor And Memory Architecture Of The Neurocomputer Synapse-1

@article{Ramacher1993MultiprocessorAM,
  title={Multiprocessor And Memory Architecture Of The Neurocomputer Synapse-1},
  author={Ulrich Ramacher and W. Raab and Joachim K. Anlauf and J. A. Ulrich Hachmann and J{\"o}rg Beichter and Nico Br{\"u}ls and Matthias Wesseling and Elisabeth Sicheneder and Reinhard M{\"a}nner and Joachim Gl{\"a}{\ss} and Andreas Wurz},
  journal={International journal of neural systems},
  year={1993},
  volume={4 4},
  pages={
          333-6
        }
}
A general purpose neurocomputer, SYNAPSE-1, which exhibits a multiprocessor and memory architecture is presented. It offers wide flexibility with respect to neural algorithms and a speed-up factor of several orders of magnitude--including learning. The computational power is provided by a 2-dimensional systolic array of neural signal processors. Since the weights are stored outside these NSPs, memory size and processing power can be adapted individually to the application needs. A neural… 
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2 References

SYNAPSE - A Neurocomputer that Synthesizes Neural Algorithms on a Parallel Systolic Engine

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    J. Parallel Distributed Comput.
  • 1992

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