Multiplierless implementation of all-pole digital filters

@article{Bhattacharya2002MultiplierlessIO,
  title={Multiplierless implementation of all-pole digital filters},
  author={M. Bhattacharya and T. Saramaki},
  journal={2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)},
  year={2002},
  volume={2},
  pages={II-II}
}
For some low sensitivity structures, the coefficient values are quite small. These values after converting them to minimum signed powers-of-two (MNSPT) or canonic signed digit (CSD) forms can be implemented in a multiplierless manner, i.e., by using only a few bit shifts and adds and/or subtracts. In such cases, the number of nonzero bits required for coefficient representations become quite low. This paper proposes a structure that is very suitable for implementing all-pole digital filters… CONTINUE READING

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