Multiplexer-based binary incrementer/decrementers

@article{Bi2005MultiplexerbasedBI,
  title={Multiplexer-based binary incrementer/decrementers},
  author={Shaoqiang Bi and Wei Wang and Asim Jawad Al-Khalili},
  journal={The 3rd International IEEE-NEWCAS Conference, 2005.},
  year={2005},
  pages={219-222}
}
In this paper, novel multiplexer (MUX)-based incrementer/decrementers are proposed. The proposed designs are more efficient in terms of speed and hardware complexity compared to the adder-based ones for both signed and unsigned cases. A FPGA implementation comparison shows that the proposed design reduces both area and delay close to 40%. The power consumed by the MUX-based design is almost 35% less than that of the carry propagation adder (CPA)-based design. 
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