Multiple reset domains verification using assertion based verification

@article{Ahmed2017MultipleRD,
  title={Multiple reset domains verification using assertion based verification},
  author={Islam Ahmed and Khaled Nouh and Amr E Abbas},
  journal={2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)},
  year={2017},
  pages={1-6}
}
Current System on Chip (SoC) designs operate in multiple domains such as clock, reset and power domains. This is done to afford various functionalities existing on different IPs that can work in different configurations. Data propagating across multiple reset domains with the absence of correct synchronizers may be corrupted and unreliable. This paper presents an efficient technique to dynamically validate multiple reset domains violations. The proposal is to first automatically model these… CONTINUE READING

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References

Publications referenced by this paper.
SHOWING 1-9 OF 9 REFERENCES

Addressing the Challenges of Reset Verification in SoC Designs

Chris Kwok, Priya Viswanathan, Ping Yeung
  • 2015
VIEW 2 EXCERPTS

Towards formal verification of reset sequence in fully asynchronous digital circuits

  • 2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
  • 2014
VIEW 1 EXCERPT

Reset Testing Made Simple with UVM Phases

B. Hunter, B. Chen, R. Lipon
  • SNUG, March 2013.
  • 2013
VIEW 1 EXCERPT

Automatic formal verification of Clock Domain Crossing signals

  • 2009 Asia and South Pacific Design Automation Conference
  • 2009
VIEW 1 EXCERPT

Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter using SystemVerilog Assertions

M. Litterick
  • DVCon, February 2006.
  • 2006
VIEW 1 EXCERPT

Fourteen ways to fool your synchronizer

  • Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings.
  • 2003
VIEW 1 EXCERPT