Multiple chip planning for chip-interposer codesign

@article{Ho2013MultipleCP,
  title={Multiple chip planning for chip-interposer codesign},
  author={Yuan-Kai Ho and Yao-Wen Chang},
  journal={2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)},
  year={2013},
  pages={1-6}
}
An interposer-based three-dimensional integrated circuit, which introduces a silicon interposer as an interface between chips and a package, is one of the most promising integration technologies for modern and next-generation circuit designs. Inter-chip connections can be routed on the interposer by chip-scale wires to enhance design quality. However, its design complexity increases dramatically due to the extra interposer interface. Consequently, it is desirable to simultaneously consider the… CONTINUE READING

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