Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction

@article{Chandra2007MultimodeIS,
  title={Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction},
  author={Anshuman Chandra and Haihua Yan and Rohit Kapur},
  journal={25th IEEE VLSI Test Symposium (VTS'07)},
  year={2007},
  pages={84-92}
}
The authors present a novel DFT technique based on multimode Illinois scan architecture (MILS) for low pin count test that simultaneously reduces test data volume and test application time. By using the proposed technique, significant savings in test data volume, and testing time can be obtained without modifying the clock tree of the design and with a very small combinational area overhead. Experimental results for two large industrial circuits show that the test data volume and test… CONTINUE READING
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