Multidimensional Intratile Parallelization for Memory-Starved Stencil Computations

@article{Malas2018MultidimensionalIP,
  title={Multidimensional Intratile Parallelization for Memory-Starved Stencil Computations},
  author={Tareq M. Malas and G. Hager and H. Ltaief and D. Keyes},
  journal={ACM Transactions on Parallel Computing (TOPC)},
  year={2018},
  volume={4},
  pages={1 - 32}
}
  • Tareq M. Malas, G. Hager, +1 author D. Keyes
  • Published 2018
  • Computer Science
  • ACM Transactions on Parallel Computing (TOPC)
  • Optimizing the performance of stencil algorithms has been the subject of intense research over the last two decades. Since many stencil schemes have low arithmetic intensity, most optimizations focus on increasing the temporal data access locality, thus reducing the data traffic through the main memory interface with the ultimate goal of decoupling from this bottleneck. There are, however, only a few approaches that explicitly leverage the shared cache feature of modern multicore chips. If… CONTINUE READING
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    References

    Publications referenced by this paper.
    SHOWING 1-3 OF 3 REFERENCES
    Cache Accurate Time Skewing in Iterative Stencil Computations
    63
    Tiling stencil computations to maximize parallelism
    94
    The pochoir stencil compiler
    311