Dynamically reducing overestimated design margin of MultiCores
Multicore processor is one of the promising techniques to satisfy computing demands of the future consumer devices. Dynamic voltage scaling (DVS) technique is a mature power reduction technique. Unfortunately, when they are combined, the efficiency in power reduction is mitigated as the number of cores on a chip increases. Furthermore, multicore processor is still threatened by increasing energy consumption due to process-voltage-temperature (PVT) variations. They require large design margins in the supply voltage, resulting in large energy consumption. This paper proposes to combine the DVS technique with a dual-sensing flip-flop (FF), named Canary FF, in order to reduce the overestimated voltage margin. We adopt Canary FF to a Toshiba's quad-core MeP and estimate its power reduction by cycle-based simulations. We find that the power consumption is reduced by 21.2%.