Multicast Test Architecture and Test Scheduling for Interposer-Based 2.5D ICs

@article{Wang2016MulticastTA,
  title={Multicast Test Architecture and Test Scheduling for Interposer-Based 2.5D ICs},
  author={Shengcheng Wang and Ran Wang and Krishnendu Chakrabarty and Mehdi Baradaran Tahoori},
  journal={2016 IEEE 25th Asian Test Symposium (ATS)},
  year={2016},
  pages={86-91}
}
Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies in a 2.5D IC must be adequately tested for product qualification. However, due to the limited number of package pins, it is a a major challenge to test 2.5 ICs using conventional methods. Moreover, due to higher integration levels, test-application time and test power consumption for 2.5D ICs are also increased compared to their 2D counterparts. Therefore… CONTINUE READING