Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect

@article{Kuznar1994MultiwayNP,
  title={Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect},
  author={Roman Kuznar and Franc Brglez and Baldomir Zajc},
  journal={31st Design Automation Conference},
  year={1994},
  pages={238-243}
}
This paper considers the problem of partitioning a large logic circuit into a collection of subcircuits each of which is implemented with a device from a specific (FPGA) library. The objective function that we minimize is not only the total cost of devices to be used in the partition but also the size of the interconnect between the devices. We introduce the concept of functional replication and a unified cost model for min-cut partitioning with replication. A prototype implementation… CONTINUE READING
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Multi-way Partitioning For Minimum Delay For Look-Up Table Based FPGAs

32nd Design Automation Conference • 1995
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