Multi-TAP connection architectures for application specific integrated circuits

In the last decade, the rapid emergence and popularity of reusable core-based designs, poses new challenges to the test-dedicated circuitry, specifically IEEE 1149.1 test access port (TAP) standard. The modern cores tend to have a build-in TAP to facilitate both on-chip design for test (DFT) and design for debug (DFD) implementation and reuse. That has… CONTINUE READING