Monolithic integration of trench vertical DMOS (VDMOS) power transistors into a BCD process

@article{Dyer2005MonolithicIO,
  title={Monolithic integration of trench vertical DMOS (VDMOS) power transistors into a BCD process},
  author={T. Dyer and Jim McGinty and Andy Strachan and C. Bulucea},
  journal={Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.},
  year={2005},
  pages={47-50}
}
  • T. Dyer, J. McGinty, C. Bulucea
  • Published 23 May 2005
  • Physics, Engineering
  • Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.
The monolithic integration of trench vertical DMOS (VDMOS) n-channel transistors into an IC BCD process is reported for the first time. The integration scheme for the trench VDMOS module is discussed and silicon results are compared with TCAD simulations. For a 50-V device, the integrated trench device is shown to offer at least a factor-of-two R/sub DS(ON)/ /spl times/ area advantage over its planar counterpart. An R/sub DS(ON)/ /spl times/ area value of 80 m/spl Omega/mm/sup 2/ is achieved… 

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