Monolithic integration of trench vertical DMOS (VDMOS) power transistors into a BCD process

  title={Monolithic integration of trench vertical DMOS (VDMOS) power transistors into a BCD process},
  author={T. Dyer and Jim McGinty and Andy Strachan and C. Bulucea},
  journal={Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.},
  • T. Dyer, J. McGinty, C. Bulucea
  • Published 23 May 2005
  • Physics, Engineering
  • Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.
The monolithic integration of trench vertical DMOS (VDMOS) n-channel transistors into an IC BCD process is reported for the first time. The integration scheme for the trench VDMOS module is discussed and silicon results are compared with TCAD simulations. For a 50-V device, the integrated trench device is shown to offer at least a factor-of-two R/sub DS(ON)/ /spl times/ area advantage over its planar counterpart. An R/sub DS(ON)/ /spl times/ area value of 80 m/spl Omega/mm/sup 2/ is achieved… 

Figures and Tables from this paper

Integrated VDMOS transistor with reduced JFET effect
In order to improve the trade-off between the breakdown voltage and the on-state resistance of integrated VDMOS transistors, an anti junction field effect implant has been introduced for an 80V smart
Integrated 60V vertical DMOS on 0.18um platform for Power over Ethernet IC
Power Management Integrated Circuits is one of the fastest growing markets in the semiconductor industry, with increasing demand for efficient electronic devices and dense integration schemes. Power
A Versatile 600V BCD Process for High Voltage Applications
A versatile 600 V BCD process using thin epitaxial technology has been realized for high voltage applications. High voltage double RESURF LDMOS with the breakdown voltage up to 900 V as well as low
60V Lateral Trench MOSFET in 0.35 μm Technology
A novel Lateral Trench MOSFET was fabricated in a 0.35 μm ModularBCDtrade technology. This device is compact, efficient, rugged, and offers hot-carrier lifetime that is far superior to equivalent
Physics, Technology, and Modeling of Complementary Asymmetric MOSFETs
The physics, technology, and modeling of complementary asymmetric MOSFETs are reviewed and illustrated with statistically representative silicon data from a recent manufacturing implementation, in
Characterization of SOA in Time Domain and the Improvement Techniques for Using in High-Voltage Integrated Circuits
  • Wen-Yi ChenM. Ker
  • Engineering
    IEEE Transactions on Device and Materials Reliability
  • 2012
Safe operating area (SOA) in power semiconductors is one of the most important factors affecting device reliability. The SOA region of power MOSFETs must be well characterized for using in circuit
A study on off-state leakage current characteristics of asymmetric-metal—oxide—semiconductor field-effect transistors
In this study, we extract the off-state current component from the asymmetric transistors in short channel 40nm DRAM. Through a quantitative comparison of λ(DIBL coefficient), we explained by
A study on off-state leakage current characteristics of asymmetric-metal-oxide-semiconductor field-effect transistors
Drain voltage has been scaled down in order to keep the power consumption under control. Hence, the threshold voltage has to be considerably scaled to maintain a high “ON” current (drive current) and


An intelligent vertical trench DMOS on SIMOX-substrate
This paper describes first results of a monolithically integrated smart power device which uses a vertical Trench-DMOS as a power switch and a signal and control circuit fabricated in a SOI-CMOS
A high current power IC technology using trench DMOS power device
A high-current power IC (PIC) technology that combines trench DMOS power devices with CMOS control is described. In the CMOS section, both high-voltage (60 V) and low-voltage (10 V) P- and N-channel
16-60 V rated LDMOS show advanced performance in a 0.72 /spl mu/m evolution BiCMOS power technology
  • C. TsaiT. Efland L. Hutter
  • Physics, Engineering
    International Electron Devices Meeting. IEDM Technical Digest
  • 1997
In this work, performance advances are featured for new and improved multi voltage rated (16 V to 60 V) LDMOS. Performance improvements were achieved by leveraging off of (1) an optimized off-set,
An improved method for determining the inversion layer mobility of electrons in trench MOSFETs
For the first time trench sidewall effective electron mobility (/spl mu//sub eff/) values were determined by using the split capacitance-voltage (CV) method for a large range of transversal effective
A 20-V p-channel with 650 /spl mu//spl Omega/-cm/sup 2/ at V/sub GS/=2.7 V: Overcoming FPI breakdown in high-channel-conductance low-V/sub t/ trenchFETs
A 5 Mcell/cm/sup 2/ (32 Mcell/in/sup 2/) low-threshold 20-V p-channel trenchFET (U-groove trench-gated DMOSFET) is reported, achieving specific on-resistances of 450, 650 and 720 /spl mu//spl
Smart power approaches VLSI complexity
The issues behind the trend to converge to a common technology platform, maintaining the peculiar aspects of power functions integration, are discussed, as well as new possible realizations in the field of super smart power ICs.
High-performance 13-65 V rated LDMOS transistors in an advanced smart power technology
A high-performance, low cost smart power technology targeting automotive applications in the 13-65 V range is described. The trade-off between on-state specific resistance and off-state breakdown
A 0.25-micron Smart Power Technology optimized for wireless and consumer applications
  • R. ZhuV. Parthasarathy D. Collins
  • Engineering
    ISPSD '03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings.
  • 2003
In this paper simultaneous optimization of 4.5-5.5V N and PMOS devices, 20-30V NLDMOS and NPN and PNP bipolar devices in a 0.25 /spl mu/m Smart Power Technology for portable wireless and consumer
Characterization of surface mobility on the sidewalls of dry-etched trenches
The mobility on the sidewalls of the etched trenches was measured for electrons and holes for two surface orientation, for two different trench etch processes, and for various post-etch treatments.