Molding Flow Modeling and Experimental Study on Void Control for Flip Chip Package Panel Molding with Molded Underfill Technology

@inproceedings{Tamil2011MoldingFM,
  title={Molding Flow Modeling and Experimental Study on Void Control for Flip Chip Package Panel Molding with Molded Underfill Technology},
  author={Jonathan Tamil and Siew Hoon Ore and Kian Yeow Gan and Yang Yong Bo and Geraldine Ng and Park Teck Wah and Dr Nathapong Suthiwongsunthorn},
  year={2011}
}
Increasing challenges are faced to ensure moldability with rapid advances in flip chip technology such as decreasing bump pitch and stand-off height, especially when commercial Moldable Underfill (MUF) is used and in particular, during panel level molding. One key challenge faced is severe void entrapment under the die. Experiments involving a large DOE matrix, which require significant time and process resources, are typically used to solve this issue. 3D flow simulation can be used to… CONTINUE READING
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