∆∑ Modulation Based On-Chip Ramp Generator for ADC BIST

Abstract

-Based on ∆∑ modulator, an on-chip analog ramp generator for ADC BIST (Built-in Self Test) is presented. Technique uses the over-sample and ∆∑ noise shaping to generate the on-chip precise analog ramp with the precise control of a calibrator of ramp slope. Moreover, because of over-sample and ∆∑ noise shaping, the design of analog circuits is simplified, and is tolerant to the mismatch of technology. Thus, the precision of the analog ramp generator is preserved. The analog ramp generator, which is implemented using a 0.18μm process from HJTC, has the 76dB SNR. It has wide output swing up to 1 voltage and maximum integral nonlinearity error (INL) of 190μV that is equivalent to 12 bits. The area overhead is 0.328mm ×0.276mm. Key-Words: ADC Self Test; Built-in-Self-Test; On-Chip Ramp Generator; ∆∑ Noise Shaping

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Cite this paper

@inproceedings{Yongsheng2005MB, title={∆∑ Modulation Based On-Chip Ramp Generator for ADC BIST}, author={Wang Yong-sheng and WANG JIN-XIANG and LAI FENG-CHANG and YE YI-ZHENG}, year={2005} }