Modular Design and Implementation of FPGA-Based Tap-Selective Maximum-Likelihood Channel Estimator

Abstract

The modular design of the optimal tap-selective maximum-likelihood (TS-ML) channel estimator based on field- programmable gate array (FPGA) technology is studied. A novel range reduction algorithm is included in the natural logarithmic function (NLF) emulator based on the coordinate rotation digital computer (CORDIC) methodology and is integrated into the… (More)

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@article{Hwang2008ModularDA, title={Modular Design and Implementation of FPGA-Based Tap-Selective Maximum-Likelihood Channel Estimator}, author={Jeng-Kuang Hwang and Yuan-Ping Li}, journal={2008 4th IEEE International Conference on Circuits and Systems for Communications}, year={2008}, pages={658-662} }