Corpus ID: 212569006

Modified VLSI Architecture for Montgomery Modular Multiplication

@inproceedings{Nto2017ModifiedVA,
  title={Modified VLSI Architecture for Montgomery Modular Multiplication},
  author={Jo{\~a}o Carlos N{\'e}to and A. Tenca},
  year={2017}
}
This paper proposes a simple and efficient Montgomery multiplication algorithm such that the low-cost and highperformance Montgomery modular multiplier can be implemented accordingly. The proposed multiplier receives and outputs the data with binary representation and uses only one-level carry-save adder (CSA) to avoid the carry propagation at each addition operation. This CSA is also used to perform operand pre computation and format conversion from the carry save format to the binary… Expand

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