Modified Montgomery modular multiplication and RSA exponentiation techniques

  title={Modified Montgomery modular multiplication and RSA exponentiation techniques},
  author={Ciaran McIvor and M{\'a}ire McLoone and John V. McCanny},
Modified Montgomery multiplication and associated RSA modular exponentiation algorithms and circuit architectures are presented. These modified multipliers use carry save adders (CSAs) to perform large word length additions. These have the attraction that, when repeatedly used to perform RSA modular exponentiation, the (carry save) format of the output words is compatible with that required by the multiplier inputs. This avoids the repeated interim output/input format conversion, needed when… 
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  • 2016
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    IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2015
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Montgomery modular exponentiation on reconfigurable hardware
  • Thomas Blum
  • Computer Science
    Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)
  • 1999
This contribution proposes arithmetic architectures which are optimized for modern field programmable gate arrays (FPGAs) and shows that it is possible to implement modular exponentiation at secure bit lengths on a single commercially available FPGA.
Asynchronous implementation of 1024-bit modular processor for RSA cryptosystem
  • Y. Kim, Wooseok Kang, J. Choi
  • Computer Science
    Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)
  • 2000
An implementation method to optimize a single-chip 1024-bit RSA processor based on the modified algorithm and architecture with 0.65-/spl mu/m SOG technology using Verilog HDL is presented.
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Each basic building block of network security is covered, including conventional and public-key cryptography, authentication, and digital signatures, as are methods for countering hackers and other intruders and viruses.