Modern floorplanning based on fast simulated annealing

  title={Modern floorplanning based on fast simulated annealing},
  author={Tung-Chieh Chen and Yao-Wen Chang},
Unlike classical floorplanning that usually handles only block packing to minimize silicon area, modern VLSI floorplanning typically needs to pack blocks within a fixed die (outline) and additionally considers the packing with block positions and interconnect constraints. Floorplanning with bus planning is one of the most challenging modern floorplanning problems because it needs to consider the constraints with interconnect and block positions simultaneously. We study in this paper two types… CONTINUE READING

19 Figures & Tables



Citations per Year

155 Citations

Semantic Scholar estimates that this publication has 155 citations based on the available data.

See our FAQ for additional information.