Modern floorplanning based on fast simulated annealing

@inproceedings{Chen2005ModernFB,
  title={Modern floorplanning based on fast simulated annealing},
  author={Tung-Chieh Chen and Yao-Wen Chang},
  booktitle={ISPD},
  year={2005}
}
Unlike classical floorplanning that usually handles only block packing to minimize silicon area, modern VLSI floorplanning typically needs to pack blocks within a fixed die (outline) and additionally considers the packing with block positions and interconnect constraints. Floorplanning with bus planning is one of the most challenging modern floorplanning problems because it needs to consider the constraints with interconnect and block positions simultaneously. We study in this paper two types… CONTINUE READING

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