Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs

Abstract

A mathematical bit error rate (BER) model for upsets in memories protected by error-correcting codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for sub-100-nm SRAM memories in space environments. Because sub-100-nm SRAM memory cells can be upset by a critical charge (Q<sub>crit</sub>) of 1.1 fC or less, they may… (More)

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