Modelling impact of digital substrate noise on embedded regenerative comparators

Abstract

This paper presents an analysis and high-level modelling method used to estimate the impact of digital substrate noise on a CMOS regenerative comparator embedded in a mixed-signal environment. A test chip was designed in a 0.35 /spl mu/m heavily doped substrate technology in order to measure the impact of digital noise on embedded CMOS regenerative… (More)

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