• Corpus ID: 18941687

Modelling and Simulation of Baseband Processor for UHF RFID Reader on FPGA

@inproceedings{IsmailModellingAS,
  title={Modelling and Simulation of Baseband Processor for UHF RFID Reader on FPGA},
  author={Ismarani Ismail and A. Ibrahim}
}
Altera, the encoder and decoder architecture is simulated to observe its functionality. The designing of the encoder and decoder is intended for uses in Ultra High Frequency (UHF) RFID passive interrogator. 
FPGA Based Decimal Matrix Code for Passive RFID Tag
TLDR
The Simulation results reveals that the Decimal Matrix Code is effective than existing Matrix and Hamming odes in terms of Error Correction Capability.
Design and Implementation of Field Programmable Gate Array Based Baseband Processor for Passive Radio Frequency Identification Tag
In this paper, an Ultra High Frequency (UHF) base band processor for a passive tag is presented. It proposes a Radio Frequency Identification (RFID) tag digital base band architecture which is

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