Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

@article{Huang2010ModelingTO,
  title={Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies},
  author={Zhangcai Huang and Atsushi Kurokawa and Masanori Hashimoto and Takashi Sato and Minglu Jiang and Yasuaki Inoue},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={2010},
  volume={29},
  pages={250-260}
}
With the scaling of complementary metal-oxide-semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis… CONTINUE READING
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