A Charge Sheet Model for the MOSFET
- JR. Brews
- Solid State Elec.,
Control gate I Select A model for static and transient simulations of an electrically erasable programmable read only memory cell has been U FG developed. This physical compact model is based on charge Source 1 1 Drain f 1 Bit line sheet approach which is able to describe the complete electrical behavior of the cell. In this model, we have introduced the dependence of the tunneling capacitance as a function of the voltage across the tunnel oxide and the floating gate depletion effect. This model has been successfully implemented in common circuit simulators and used for the study of the write/erase operations in a memory cell. The simulations compared to the experimental results are in good agreement.