Modeling of a floating-gate EEPROM cell using a charge sheet approach including variable tunneling capacitance and polysilicon gate depletion effect

Abstract

Control gate I Select A model for static and transient simulations of an electrically erasable programmable read only memory cell has been U FG developed. This physical compact model is based on charge Source 1 1 Drain f 1 Bit line sheet approach which is able to describe the complete electrical behavior of the cell. In this model, we have introduced the dependence of the tunneling capacitance as a function of the voltage across the tunnel oxide and the floating gate depletion effect. This model has been successfully implemented in common circuit simulators and used for the study of the write/erase operations in a memory cell. The simulations compared to the experimental results are in good agreement.

DOI: 10.1109/ISCAS.2001.922364

Cite this paper

@inproceedings{Bouchakour2001ModelingOA, title={Modeling of a floating-gate EEPROM cell using a charge sheet approach including variable tunneling capacitance and polysilicon gate depletion effect}, author={Rachid Bouchakour and N. Harabech and Pierre Canet and Ph. Boivin and J. M. Mirabel}, booktitle={ISCAS}, year={2001} }