Modeling of Quantum Confinement and Capacitance in III–V Gate-All-Around 1-D Transistors

@article{Ganeriwala2017ModelingOQ,
  title={Modeling of Quantum Confinement and Capacitance in III–V Gate-All-Around 1-D Transistors},
  author={Mohit D. Ganeriwala and Chandan Yadav and Francisco J. Garcix0301a Ruiz and Enrique G. Marin and Yogesh Singh Chauhan and Nihar Ranjan Mohapatra},
  journal={IEEE Transactions on Electron Devices},
  year={2017},
  volume={64},
  pages={4889-4896}
}
In this paper, a physics-based compact model for calculating the semiconductor charges and gate capacitance of III–V nanowire (NW) MOS transistors is presented. The model calculates the subband energies and the semiconductor charges by considering the wave function penetration into the gate insulator, effective mass discontinuity at the semiconductor–oxide interface, 2-D confinement in the NW, and Fermi–Dirac statistics. The semiconductor charge expression proposed in this paper is completely… CONTINUE READING

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