Modeling of DDR5 signaling from jitter sequences to accurate bit error rate (BER)

Intel's signal integrity (SI) analysis for memory in the server segment has neither considered correlated jitter nor handled jitter amplification over channel when performing fast analytical signaling analyses. This inaccuracy is no longer feasible with the intended data rates of DDR5. Here, we propose a DDR5 flow that starts from jitter sequences or… CONTINUE READING