Corpus ID: 17664042

Modeling of Booth Radix-4 Floating Point Multiplier for VLSI Designer ’ s Library

@inproceedings{Pang2014ModelingOB,
  title={Modeling of Booth Radix-4 Floating Point Multiplier for VLSI Designer ’ s Library},
  author={W. Pang and Kah-Yoong Chan and S. Wong and CHOON-SIANG Tan},
  year={2014}
}
Floating point arithmetic computation has been widely used today in graphics, digital signal processing, image processing and other applications. Multiplication is the most complex calculation that used in most digital electronic circuit. The multiplier may have large chip area density, high complexity, and is a time consuming computation because the output data size is twice larger than input data size. Complex floating point multiplication required more time to process data and is highly… Expand

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References

SHOWING 1-10 OF 13 REFERENCES
Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier
  • M. Jaiswal, R. Cheung
  • Computer Science
  • 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum
  • 2012
A parallel IEEE P754 decimal floating-point multiplier
VHDL Modelling of Reed Solomon Decoder
A Suggestion for a Fast Multiplier
A FPGA Floating Point Interpolator
VHDL modeling of the IEEE802.11b DCF MAC
Onisifor, A FPGA Floating Point Interpolator
  • Advances in Intelligent Systems and Computing,
  • 2013
VHDL environment for pipeline floating point arithmetic logic unit design and simulation
...
1
2
...