Modeling and verifying hierarchical real-time systems using stateful timed CSP

@article{Sun2013ModelingAV,
  title={Modeling and verifying hierarchical real-time systems using stateful timed CSP},
  author={Jun Sun and Yang Liu and Jin Song Dong and Yan Liu and Ling Shi and {\'E}tienne Andr{\'e}},
  journal={ACM Trans. Softw. Eng. Methodol.},
  year={2013},
  volume={22},
  pages={3:1-3:29}
}
Modeling and verifying complex real-time systems are challenging research problems. The de facto approach is based on Timed Automata, which are finite state automata equipped with clock variables. Timed Automata are deficient in modeling hierarchical complex systems. In this work, we propose a language called Stateful Timed CSP and an automated approach for verifying Stateful Timed CSP models. Stateful Timed CSP is based on Timed CSP and is capable of specifying hierarchical real-time systems… CONTINUE READING
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