Modeling and extraction of interconnect capacitances for multilayer VLSI circuits

@article{Arora1996ModelingAE,
  title={Modeling and extraction of interconnect capacitances for multilayer VLSI circuits},
  author={Narain D. Arora and Kartik V. Raol and Reinhard Schumann and Llanda M. Richardson},
  journal={IEEE Trans. on CAD of Integrated Circuits and Systems},
  year={1996},
  volume={15},
  pages={58-67}
}
We report an accurate and practical method of estimating interconnect capacitances for a given circuit layout. The method extraction of the complete circuit level capacitances at each node in the circuit. The layout geometry is reduced into base elements that consist of different vertical profiles at each node in the layout. Accurate analytical models are developed for calculating capacitances of structures using a 2-D capacitance simulator TDTL. These are then transformed into 3-D geometry… CONTINUE READING
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“ OPTIMA : 4 nonlinear model parameter extraction program with confidence region algorithms

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